Dual-addressed rectifier storage device

ABSTRACT

A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.09/821,182, filed Mar. 29, 2001, now U.S. Pat. No. RE41,733, which is areissue of U.S. patent application Ser. No. 08/863,156, filed May 27,1997, now U.S. Pat. No. 5,889,694, which is a continuation-in-part ofU.S. patent Application Ser. No. 08/610,992 entitled “Dual AddressedRectifier Storage Device”, filed Mar. 5, 1996, now U.S. Pat. No.5,673,218, issued Sep 30, 1997. Reissue application Ser. No. 11/780,300,filed Jul. 19, 2007 is also a resissue of U.S. Pat. No. 5,889,694. Theentire disclosure of each of these applications is hereby incorporatedby reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electronic data retrieval devices, andmore particularly to electronic digital logic devices havingsemiconductor mass storage capabilities by virtue of their data beingstored in highly symmetrical arrays of diodes.

2. Prior Art

Most present day devices having mass storage capabilities rely on suchmoveable media as magnetic disks, optical compact disks, digital tape orthe like. Some devices having large storage Capabilities have utilizedlarge numbers of read-only memory (ROM) devices.

Many read-only memory (ROM) devices have been disclosed having a widevariety of implementations. In many of these devices the bit storagemeans is accomplished through the application of gates or transistors.But, a subset of these ROM devices has accomplished the bit, storagemeans through the use of a matrix of diodes, as was disclosed by Robb inU.S. Pat. No. 3,245,051. Many of these ROM device is include diodematrix storage means utilizing a set of conductors that act as selectorsand a second orthogonal set of conductors that act as data outputs.

In U.S. Pat. No. 4,070,654, one set of generally parallel conductorsacts as the Selection Input Lines and a second set of generally parallelconductors that is orthogonal to and overlapping with the first acts asthe Digit Output Lines. A bit of information is represented at eachpoint of intersection of the Selection Input lines with the Digit OutputLines by the presence or absence of a diode at that point, where thepresence or absence of a diode distinguishes the logical state of thestored information bit at that point of intersection. A selectioncircuit selects one line of the Selection Input Lines such that thestate of all of the Digit Output Lines is then controlled to the extentthat each of those Digit Output Lines is connected to that selectedSelection Input Line through a diode. All of the digit Output Lines areread in parallel. A disadvantage is that as the matrix is increased insize, the complexity of the selection logic that drives the selectioncircuits (such that one line is selected out of the many Selection InputLines) grows exponentially. But as this matrix increases in size, so toowill the number of Digit Output Lines that will have to besimultaneously supplied with current and that current will varydepending upon the state of the bits at those various locations. Also,as the number of simultaneously driven Digit Output Lines increases,some means of selecting the subset of desired data bits would have to beadded.

In U.S. Pat. No. 4,661,927, some of the problems of the exponentialgrowth in the complexity of the addressing circuitry and of the loadingon the selected addressing lines are dealt with. Addressing isaccomplished by using diode-transistor logic (DTL) for the inputaddressing. The transistors of the DTL selection circuits act asbuffer-drivers between the address selection means and the bit storagemeans thereby providing the current needed to source a growing number ofdata bit output lines. However, the transistors in this DTL circuitryadd complexity to the overall circuit which will reduce packingdensities and add an additional problem—that of leakage currents inthose transistors—that requires additional compensating circuitry thatfurther reduces packing densities. The use of dummy diode loads forbalancing data dependent loading variations reduces packing densitieseven further.

In U.S. Pat. No. 4,884,238, the problem of loading is dealt with byutilizing FET switches to disconnect all but the desired Digit Outputline. The selected bit is present at the intersection of two selectedorthogonal conducting lines. In this way, the number of bitssimultaneously selected does not grow with the size of the array and theproblem of loading can be controlled. But, such a design still requiresa large number of FET transistors and the addressing means to controlthose FET transistors and the interconnection wiring to connect saidaddressing means with said FET transistors which will reduce packingdensities. While the addressing means could be of the same DTL type tokeep said addressing means small, the large number of bufferingtransistors to select the various conductive lines will remain large (atleast one FET per conductive line and, on about half of the lines, twoFET's). Furthermore, this inclusion of FET transistors may make thedevice subject to damage from static electrical discharges that mightmake it less practical for use in a consumer product where the consumermay handle these devices.

In U.S. Pat. No. 4,347,585, Eardley discloses a dual-addressed devicewherein the selected diode is at the intersection of a column line and arow line (where the column lines are connected to the diodes' cathodesand the row lines are connected to the diodes' anodes) such that thevoltage potential of one column line is lowered and the voltagepotential of one row line is raised thereby forward biasing the diode,if any, at the point of intersection of the two lines. One of thefeatures of this device over the prior art (as discussed in that patent)is the circuitry for the selection logic; Eardley discloses means forline selection comprising high speed transistor driver circuits. Thedisclosed device also requires two types of Schottky barrier diodedevices. As a result, it is anticipated that the disclosed device willsuffer from several problems, particularly when one attempts to scale upthe device to extremely high storage densities. These problems mayinclude transistor current leakage becoming noticeable as the number oftransistors increases and device yields becoming reduced as thecomplexity of multiple semiconductor fabrication steps and nore complexdevice interconnect circuitry increases. These problems may prevent thekind of size scaling that could result in devices in the Gigabit rangethat would be necessary to create memory chips that could replacetoday's CD-ROMs.

As will be shown below, the Dual-addressed Rectifier Storage DRS) Arraycomprised by the present invention solves many of the Problemsassociated with the above mentioned inventions while staining high datapacking densities by simultaneously using both orthogonal sets ofconductors to address the data bits without the need for transistorswitches on each conductive line. It does this by having a diode-logicaddressing mechanism directly controlling the voltage levels on theconductive lines. Also, by extending the application of the diode arrayto perform the functions of addressing, storage, and bit sensing,symmetry is increased and this higher symmetry results in higher packingdensities.

In U.S. Pat. No. 4,070,654, among others, a means is disclosed forprogramming the information into a semiconductor diode array byselectively etching away openings through the oxide layer that insulatesthe plurality of doped conductors from the orthogonal plurality ofmetalized conductors on the surface such that each opening enabledcontact between the respective conductor of each plurality therebyforming a diode representing a toggled bit of stored information at thatarray location. The present invention discloses a means for constructingthe semiconductor device up to the final metalization etch step beforeprogramming the data thereby enabling the programming of data to beperformed much later in the manufacturing process.

Mass storage devices comprising moveable media such as magnetic disks,optical compact disks, digital tape, or the like, have motors and othermechanical parts that are prone to breaking or wearing out, can sufferaudio disruption when subjected to vibrations, are too heavy to becarried during certain activities such as jogging, and consumesignificant electrical power (due to the operation of the mechanicalcomponents). Devices utilizing ROM chips are limited in their capacitiesdue to the limited storage densities of present day ROM chips. Thepresent invention eliminates or reduces all of these drawbacks becauseit uses DRS Arrays and, as a result, has the high storage densities of aCD-ROM without having mechanical parts.

SUMMARY OF THE INVENTION

Instead of a CD-ROM and its associated mechanical components, thisdevice comprises one or more Dual-addressed Rectifier Storage (DRS)Arrays which are read-only memory (ROM) devices that utilize an array ofrectifiers for its storage means. Like the predecessors to the DRSArray, the logical state of stored data is determined by the presence orabsence of rectifiers at the points of intersection of two orthogonaland overlapping sets of generally parallel conductive lines. The presentinvention uses both sets of generally parallel conductive lines foraddressing but senses the logical state of the addressed data by sensingthe loading on the selected lines.

The DRS Array comprises a cross-point selection means that enables theselection of a single point of intersection from within an array byapplying a forward voltage across that point; this selection means willfind applications in Read Only Memory (ROM) as shown in the presentdevice, One-Time Programmable Read Only Memory (OTPROM), Random AccessMemory (RAM), and LED matrix displays.

More specifically, the DRS Array comprises an array of Rectifiers (wherethe column lines are connected to the cathodes of said rectifiers andthe row lines are connected to the anodes of said rectifiers) whereinthe row lines and column lines are pulled through resistive means toeither the positive supply or to ground, respectively, such that, absentany addressing circuitry, all of the rectifiers in the array would beforward biased. The addition of addressing circuitry will selectivelyconnect those row lines and column lines to either ground or thepositive supply such that the voltage potential between any row line andcolumn line would be dropped to the point that an interconnectedrectifier no longer would be forward biased. Any line whose voltage ispulled close to either ground or to the positive supply and away fromthat voltage that would result from the resistive means alone will bereferred to as Being “disabled.”

Selection of a line in both sets of generally parallel lines isaccomplished by a diode addressing array similar to that disclosed inU.S. Pat. No. 4,661,927 but, instead of using diode-transistor logic(DTL) means to do this addressing, no transistor buffer-driver stage isused, thereby greatly reducing circuit complexity while eliminating asource of possible current leaks. This is possible by taking advantageof the forward voltage drop characteristics of a rectifier to controlthe voltage levels. The present device does not attempt to drive aheavily loaded selected line (where all of the orthogonal output linesthat are connected to the selected line through diodes comprise thatloading) that might require such a buffer-driver stage; the only load isthat rectifier connection to the selected orthogonal line. One result ofthis disabling means is a greatly simplified selection circuit on bothorthogonal sets in the array. The addressing means, the storage means,and the bit sensing means are all formed in the same rectifier arraystructure in a highly simple and symmetric design that is ideal for highpacking densities.

The present invention comprises DRS Arrays that could be removable andinterchangeable so that one could pop them in and out according to theircurrent musical interest or desire. A DRS Array is expected to be ableto hold the equivalent of an entire CD-ROM or more on a single one inch(or smaller) square of silicon, unlike conventional read only memorychips (ROM's) which would require about 50 ROM chip if each containedabout 10 Megabytes of data. By contrast, the present invention would bevery small and compact.

While most present day mass storage devices rely on such moveable mediaas magnetic disks, optical compact disks, digital tape or the like, thepresent invention, through the use of the DRS array, eliminates themechanical components of such devices. In so doing, the presentinvention reduces the risk of mechanical failures, the problems ofbulkiness, and the consumption of electrical power. The many possiblevariations on the DRS Array make it a very versatile storage mediumranging from a stand-alone array chip, to an array chip with anincorporated sequentially loaded address sequencer, to a microcomputerchip that utilizes the DRS Array for its program memory, to a personalstereo unit utilizing a removable DRS Array instead of a music CD-ROM,to a pocket sized video player utilizing a removable DRS Array modulecontaining compressed video data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1. illustrates a block diagram of a digital logic device comprisinga Dual-addressed Rectifier Storage (DRS) Array, keypad, CD display anddual analog outputs.

FIG. 2. illustrates a schematic diagram showing one way to interface aDual-addressed Rectifier Storage Array to a digital logic device.

FIG. 3. illustrates a schematic diagram of a Dual-addressed RectifierStorage Array.

FIG. 4. illustrates a schematic diagram of a Dual-addressed RectifierStorage Array which includes complementary address selection circuitry.

FIG. 5. illustrates a variation on the data sensing means of aDual-addressed Rectifier Storage Array for simultaneously accessingmultiple stored bits in parallel and a variation on the addressing meansfor reducing the device's power consumption.

FIG. 6. illustrates the doping step in the semiconductor manufacture ofthe Anode Lines, Cathode Lines, and rectifiers comprised by aDual-addressed Rectifier Storage Array.

FIG. 7. illustrates the oxide growth step in the semiconductormanufacture of the Anode Lines, Cathode Lines, and rectifiers comprisedby a Dual-addressed Rectifier Storage Array.

FIG. 8. illustrates the oxide etch step in the semiconductor Manufactureof the Anode Lines, Cathode Lines, and rectifiers comprised by aDual-addressed Rectifier Storage Array.

FIG. 9. illustrates the metalization step in the semiconductorManufacture of the Anode Lines, Cathode Lines, and rectifiers comprisedby a Dual-addressed Rectifier Storage Array.

FIG. 10. illustrates the metalization etching step in the semiconductormanufacture of the Anode Lines, Cathode Lines, and rectifiers comprisedby a Dual-addressed Rectifier Storage Array.

FIG. 11. illustrates a variation on the semiconductor manufacture of theAnode Lines, Cathode Lines, and rectifiers comprised by a Dual-addressedRectifier Storage Array.

FIG. 12. illustrates a plot of the voltage/current relationship of adiode.

FIG. 13. illustrates a schematic diagram of a variation on theDual-addressed Rectifier Storage Array wherein the resistive means isaccomplished via “leaky” diodes.

FIG. 14. illustrates a schematic diagram of a variation on theDual-addressed Rectifier Storage Array which includes serial addressingcircuitry.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Refer now to the drawings which show a preferred embodiment of theinvention. FIG. 1 shows a block diagram of a digital logic devicecomprising a microcomputer, a keypad, an LCD display, analog to digitalconverters, analog buffers and amplifiers, a headphone jack, and aDual-addressed Rectifier Storage (DRS) Array. Microcomputer, A, isconnected to a keypad, B, and an LCD display, C. This configuration isvery common and several of the manufacturers of microcomputer chips haveapplication notes showing the details and schematics of such a circuitconfiguration. Microcomputer, A, is also interfaced to two 16 bitdigital to analog converters, E, whose outputs are connected tocircuitry, F, capable of driving a set of headphones (plugged into thisdevice at the headphone jack, G). Circuitry such as this just describedis known by one skilled in the art; this circuitry exists in essentiallythis form in many common devices, including portable CD-ROM audioplayers used for listening to music CD's.

Software running in the microcomputer, A, would cause that microcomputerto sequentially read 4 bytes of data from the DRS Array, D, every 25μSec and move that data to the two 16-bit digital to analog converters,E. The result of this process would be 16 bit stereo sampled at 40 KHzthereby matching the audio of current CD-ROM technology. Softwarerunning in the microcomputer could also cause information read from theDRS Array (such as musical artist, title of the audio tracks, playingtime, and the like) to be displayed on the LCD display. Software runningin the microcomputer could also read from the keypad to affect theoperation of that running software and cause it to jump to a specificaddress in the DRS Array at which point it would continue to readsequentially (such as to skip or repeat certain audio tracks, play thetracks contained in the DRS Array in random order, or the like).

The data contained in the DRS Array need not be limited to musical data.Video data, computer software or applications, reference data such astext, diagrams or the like, or a variety of other information could bestored. Of course, in many of these possible data types, the exactconfiguration as shown in FIG. 1 may not be needed. for example, a DRSArray containing computer software would likely not need two digital toanalog converters for output but would rather need interface logic suchthat it could be connected to a standard computer such that it emulateda standard CD-ROM drive. In this way, one could enjoy the benefitsafforded by the use of DRS arrays without having to modify one'sstandard computer or its software (given an accurate emulation of aCD-ROM drive, that standard computer would operate just as if it wasactually connected to a CD-ROM drive). What is needed is the ability toconnect DRS Arrays to such digital logic devices as a personal computer,a microprocessor, a microcomputer chip or the like.

Refer now to FIG. 2 which shows a possible way to interface aDual-addressed Rectifier Storage Array to a digital logic device. Onmicroprocessor, A, the address lines (or input/output ports configuredto perform the function of addressing), A0 through A15, connect directlyto the lower address lines, A0 through A15, of the DRS Array, as well asto the inputs of the 16 bit latch, H. The upper 16 bits of the addressto the DRS Array are set by writing to a location in memory having thesame lower 16 address bits as is desired for the upper address bits.When the write line, −WR, goes low and, at the end of that write cycle(when that write line goes back high), that rising edge will cause theaddress bits A0 through A15 to be latched in the 16 bit latch, H, wherethey will be held to address the upper address lines of the DRS Array,A16 through A31, until the next write cycle. Note that the data bytewritten is ignored, only the address bits are needed to set the latch.(A variation would be to make use of that data byte to control theselection of multiple DRS Arrays or to address additional address bitsof an even larger DRS Array. Other techniques for latching additionalselection bits are readily known by those skilled in the art if multipleDRS Arrays are to be interfaced. Of course, if the digital logic devicewas a microprocessor having an addressing port sufficiently wider thanthe 16 bits shown in this figure, then the latching mechanism would beunnecessary as the entire DRS Array might be addressed directly.) TheDRS Array is configured to be enabled by applying power through PNPtransistor, I, and resistor, J, when the read line, −RD, goes low. TheDRS Array as shown in FIG. 2 would contain about 537 Megabytes ofinformation or about 56 minutes of 16-bit stereo audio sampled at 40,000KHz, roughly the equivalent of a present day CD-ROM.

Throughout the remainder of this description, references will made tothe positions of different parts of the DRS Array; this is for ease oflooking at the figures only, and is not meant to imply physical locationof components in an actual device. Also in this description, transistorsin the fully on state will be referred to as being saturated. Switchingtransistors into and out of saturation is typically slower thanswitching them into and out of a nearly saturated state (although nearlysaturated will generally work as well). Circuitry to keep transistorsfrom becoming fully saturated is desirable but not required and has beenomitted for the purpose of keeping the descriptions and figuresuncluttered.

Refer now to FIG. 3 which illustrates an example of a preferredembodiment of a Dual-addressed Rectifier Storage Array. While the arrayin this example is only 64 bits in size, it will become clear to oneskilled in the art that this array is highly scaleable.

Rows are drawn running horizontally in this figure and Columns are drawnrunning vertically. The Storage Rows, P, are connected to the RowResistors, R. Also connecting to the Storage Rows, P, at various pointsare the anodes of the Storage Rectifiers, K, the anodes of the RowAddressing Rectifiers, L, and the anodes of the Storage Bit SensingRectifiers, U. Connecting to the Addressing Columns, N, are the cathodesof the Row Addressing Rectifiers, L. Connecting to the Storage BitSensing Column, M, are the cathodes of the Storage Bit SensingRectifiers, U.

The Storage Columns, O, are connected to the Column Resistors, S. Alsoconnecting to the Storage Columns at various points are the cathodes ofthe Storage Rectifiers, K, and the cathodes of the Column AddressingRectifiers, T. Connecting to the Addressing Rows, Q, at various pointsare the anodes of the Column Addressing Rectifiers, T.

To understand the operation of the device, first consider what theoperation of the device would be absent the row addressing means (theRow Addressing Rectifiers, L, and the Addressing columns, N) and thecolumn addressing means (the Column addressing Rectifier, T, and theAddressing Rows, Q) and the bit sensing means (the Storage Bit SensingRectifiers, U, and the storage Bit Sensing Column, M). What would beleft are the Storage Rows, P, which are each pulled to the positivesupply through the Row Resistors, R, and the Storage Columns, O, whichare each pulled to ground through the Column Resistors, S. The resultwould be that any rectifier present among the Storage Rectifiers, K,would be forward biased and the forward voltage drop of any said Storagerectifier would be centered around the voltage level of one-half of thepositive supply (the Row Resistors, R, and the Column Resistors, S, areof equal resistance values and therefore form a voltage divider having acenter voltage level of one-half of the positive supply). The resistivemeans, Row Resistors, R, and the Column Resistors, S, could beconstructed through the use of resistors or their equivalent, the use oftransistors (bipolar or FET) biased in their linear region (betweenbeing completely turned off and being saturated), the use of “leaky”diodes, or the like.

Next, consider the impact of the Row Addressing Rectifiers, L, and theAddressing Columns, N. The Addressing Columns, N, work in complementarypairs labeled by address designation An and its complement −An (where nindicates the Nth address line). Addressing is performed by pulling anAddressing Column near to ground or near to the positive supply and itscomplementary Addressing Column near to the positive supply or near toground respectively. (Allowing an Addressing Column to float instead ofpulling it close to the positive supply would work, too.) When anAddressing Column is pulled near to ground, any of the Row AddressingRectifiers whose cathodes are connected to said Addressing Column willbe forward biased and the voltage drop across those rectifiers willdetermine the resulting voltage on the Storage Rows connected to saidforward biased Row Addressing Rectifiers. Storage Rows whose voltagesare pulled down in this way are called “disabled.” The voltage level onsaid disabled Storage Rows would be equal to the near to ground voltageon the Addressing Column plus the forward voltage across said forwardbiased Row Addressing Rectifier.

Next, consider the impact of adding the Column Addressing rectifiers, T,and the Addressing Rows, Q. The Addressing Rows, Q, work incomplementary pairs labeled by address designation An and its complement−An (where n indicates the Nth address line). addressing is performed bypulling an Addressing Row near to ground or near to the positive supplyand its complementary Addressing Row near to the positive supply or nearto ground respectively. (allowing an Addressing Row to float instead ofpulling it close to ground would work, too.) When an Addressing Row ispulled to the positive supply, any of the Column Addressing Rectifierswhose anodes are connected to said Addressing Row will be forward biasedand the voltage drop across those rectifiers will determine theresulting voltage on the Storage Columns connected to said forwardbiased Column Addressing Rectifiers. Storage Columns whose voltages arepulled up in this way are called “disabled.” The voltage level on saiddisabled Storage Column would be equal to the near to the positivesupply voltage on the Addressing Row minus the forward voltage acrosssaid forward biased Column Addressing Rectifier.

Disabling the Storage Rows by pulling their voltages down and disablingthe Storage Columns by pulling their voltages up will reverse bias anyStorage Rectifiers at the intersection of said disabled Storage Rowswith said disabled Storage Columns. The Storage Rectifier, if any, atthe intersection of the remaining enabled Storage Row with the remainingenabled Storage Column will be forward biased and the forward voltagedrop of said Storage Rectifier, if any, would be centered around thevoltage level of one-half of the positive supply. This would place thevoltage level on the enabled Storage Row at one-half of the positivesupply plus one-half of the forward voltage drop across said StorageRectifier. Also, this would place the voltage level on the enabledStorage Column at one-half of the positive supply less one-half of theforward voltage drop across said Storage Rectifier. If no StorageRectifier was present at the intersection of the remaining enabledStorage Row with the remaining enabled Storage Column then the voltageon that enabled Storage Row would be the positive supply and the voltageon that enabled Storage Column would be ground. (It should be noted thatit does not matter if the storage rectifiers between the disabled rowsand the disabled columns are forward biased because, as will be seenbelow, the storage bit sensing circuitry will not sense those Rows thathave been shifted to the disabled voltage level.)

The Storage Bit Sensing Column, M, is to be biased to a voltage leveljust below the positive supply minus one rectifier forward voltage drop.Recalling that a disabled Storage Row will be at a voltage level equalto a near to ground voltage plus a rectifier's forward voltage, thismeans that the Storage Bit Sensing Rectifiers, U, between the StorageBit Sensing Column, M, and each of the disabled Storage Rows will bereverse biased and conduct no current; this will account for the stateof all of the Storage Bit Sensing Rectifiers, U, except the oneconnected between the Storage Bit Sensing Column, M, and the one enabledStorage Row. If a rectifier is present at the intersection of theenabled Storage Row with the enabled Storage Column then that enabledStorage Row, then the voltage level on that enabled Storage Row would beat one-half of the positive supply plus one-half of a rectifier'sforward voltage which would not be sufficient to forward bias theStorage Bit Sensing RectiFier and no current will flow to the output,OUT. On the other hand, if no rectifier is present at the intersectionof the enabled Storage Row with the enabled Storage Column then thatenabled Storage Row, absent any Storage Bit Sensing Rectifier, would beat the Voltage potential of the positive supply; this is sufficient toforward bias the Storage Bit Sensing Rectifier and current will flow tothe output, OUT. Naturally, this assumes that the voltage level of thepositive supply is sufficiently high to forward bias the variousrectifiers as described. Also, it is preferable to keep the positivesupply to as low a voltage as possible in order to minimize powerdissipation and to minimize the reverse voltages on the Storage BitSensing Rectifiers, U, thereby reducing the potential current leakagethrough those Storage Bit Sensing Rectifiers that might tend to offsetthe output current. This leakage current would be fairly constant andequal to the leakage of a rectifier reverse biased by an amount equal tothe difference between the bias voltage on the output and the voltage ona disabled Storage Row multiplied by the number of disabled Storage Rowsand, as such, could be corrected for if necessary. For example, anopposite current of equal magnitude could be injected into the StorageBit Sensing Column.

As shown in FIG. 3, to the left of each Storage Row, P, is an addressdesignation shown as an “X” followed by some binary digits. The “X”signifies the upper address bit inputs (which control the AddressingRows, Q,) and the binary digits signify the lower address Bit inputswhich control the Addressing Columns, N. As is shown, for each addressbit input there are two Addressing Columns—one corresponding directly tothe address bit input (labeled An) and one corresponding to thecomplement of that address bit input (labeled −An). Each bit position inthe address designation of any Storage Row corresponds to a givenaddress bit input and to a complementary pair of Addressing Columns.When the bit position contains a 0, a rectifier is connected betweenthat Storage Row and the Addressing column corresponding to thecomplement of that address bit input. when the bit position contains a1, a rectifier is connected between that Storage Row and the AddressingColumn corresponding directly to that address bit input.

Also as shown in FIG. 3, below each Storage Column, O, is an addressdesignation shown as some binary digits followed by an “X”. The “X”signifies the lower address bit inputs (which control the addressingRows, N) and the binary digits signify the upper address bit inputswhich control the Addressing Rows, Q. As is shown, for each address bitinput there are two Addressing Rows—one corresponding directly to theaddress bit input (labeled An) and one corresponding to the complementof that address bit input (labeled −An). Each bit position in theaddress designation of any Storage Column corresponds to a given addressbit input and to a complementary pair of Addressing Rows. When the bitposition contains a 0, a rectifier is connected between that StorageColumn and the Addressing Row corresponding directly to that address bitinput. When the bit position contains a 1, a rectifier is connectedbetween that Storage Column and the Addressing Row corresponding to thecomplement of that address bit input.

Refer now to FIG. 4 which shows identical circuitry to that shown inFIG. 3 except for the addition of complementary address inputbuffer-driver circuitry, V, W, X, and Y, as well as an output drivercircuit, Z. Following the addressing of one complementary pair ofaddressing transistors controlled by address line A2, one will see thattransistors Q2 and Q4 will be turned off through resistors R10 and R12when A2 is at a low logic state (a low enough voltage that the baseemitter junctions of Q2 and Q4 are not forward biased) or floating. Whentransistor Q4 is turned off, transistor Q3 will be turned on by thepositive supply through resistor R11. One will also see that transistorsQ2 and Q4 will be turned on through resistors R10 and R12 when A2 is ata high logic state. When Transistor Q4 is turned on, it will pull awaythe current available at the base of Q3, dropping the voltage on thebase of Q3 and thereby turning off Q3. The result is that the directlyaddressed Addressing column, A2, will be pulled to near ground(approximately 0.2 v) when A2 is low and Q3 is turned on (saturated), orthe complementary addressed Addressing Column, −A2, will be pulled tonear ground (approximately 0.2 v) when A2 is high and Q2 is turned on.

Following the addressing of another complementary pair of addressingtransistors controlled by address line A3, one will see that transistorsQ11 and Q12 will be turned off through resistors R19 and R20 when A3 isat a high logic state (a high enough voltage that the base emitterjunctions of Q11 and Q12 are not forward biased) or floating. Whentransistor Q11 is turned off, transistor Q13 will be turned on throughresistor R21 to ground. One will also see that transistors Q11 and Q12will be turned on through resistors R19 and R20 when A3 is at a lowlogic state. When transistor Q11 is turned on, it will cause the voltageon the base of Q13 to come within 0.2 v of the positive supply andthereby turning off Q13. The result is that the complementary addressedAddressing Row, −A3, will be pulled to within 0.2 v of the positivesupply when A3 is low and Q12 is turned on, or the directly addressedAddressing Row, A3, will be pulled to within 0.2 v of the positivesupply when A3 is high and Q13 is turned on.

The output driver circuit, Z, achieves the voltage biasing of theStorage Bit Sensing Column, M, while providing gain to the outputcurrent. The three rectifiers, D33, D34, and D35, serve to set thevoltage on the emitter of transistor Q1 at three rectifier forwardvoltage drops below the positive supply. Assuming that the forwardvoltage drop across the base-emitter junction of transistor Q1 is thesame as the forward voltage drop of the rectifiers, this would requirethat the base of that transistor be at a voltage level no less than tworectifier forward voltage drops below the positive supply in order forits collector to draw current, which in turn would require that the oneenabled Storage Row be at a voltage level no less than one rectifierforward voltage drop below the positive supply in order for thecollector of transistor Q1 to draw current. Naturally, it is notnecessary that the forward voltage drop across the base-emitter junctionof transistor Q1 would be the same as the forward voltage drop of therectifiers and one skilled in the art will know of other ways to biasthe Storage Bit Sensing Column.

The circuit used to describe the operation of a DRS Array and shown inFIG. 4 can be constructed using silicon diodes (such as the 1N914) forall of the rectifiers; 1 MΩ resistors for all of the Row Resistors, R,and Column Resistors, S, and for the resistor in the output drivercircuit, R9; 10KΩ resistors for all of the resistors of the addressinput buffer-driver circuitry, V and W; 2N3904 transistors for all ofthe NPN transistors and 2N3906 transistors for all of the PNPtransistors. The output will sink virtually no current when addressingthe point of intersection of a Storage Row with a Storage Column thathas a rectifier present at that point. If no rectifier is present at theaddressed point of intersection, approximately 0.7 μA will flow into thebase of Q1 and, assuming a current gain (β) of about 100 times for Q1,the output will therefore sink abouto 0.07 mA.

Some variation on this idea will be apparent. FIG. 5 shows twovariations on the Dual-addressed Rectifier Storage Array. The firstvariation relates to the number of bits of stored information that willbe retrieved at the same time. Notice that Row Addressing Rectifiers D9through D16, transistors QZ through Q4 and resistors R10 through R12have been removed, that transistor Q23, rectifiers D86, D87, and D88 andresistor R39 have been added, and that the Storage Bit SensingRectifiers have been split into two groups where the cathodes ofrectifiers D5 through D8 are now connected to the base of transistor Q23through a new Storage Bit Sensing Column. The resulting circuit is theequivalent of two DRS Arrays placed one above the other with each havingfour Storage Rows and eight Storage Columns where those eight StorageColumns (and their associated addressing means) are common to botharrays and where the Addressing Columns that are connected to thecathodes of the Row Addressing Rectifiers of the two arrays (and theirassociated addressing means) are also common to both. Transistor Q1,rectifiers D33, D34, and D35, and resistor R9 now operate with StorageBit Sensing Rectifiers, D1, D2, D3, and D4, to detect state of theaddressed bit within one array and transistor Q23, rectifiers D86, D87,and D88, and resistor R39 now operate with Storage Bit SensingRectifiers, D5, D6, D7, and D8, to detect state of the addressed bitwithin the other array. In this way, two bits—one from one array and onefrom the other array—will be read out at the same time. One skilled inthe art will recognize that this variation can be applied multiple timessuch that even larger numbers of bits can be read simultaneously.

Also shown in FIG. 5 is a variation relating to the power requirementsof the device and, in particular, to limiting the current in the deviceto only a portion of that device thereby reducing the overall powerconsumption. Notice that Column Addressing Rectifiers D36 through D43,transistors Q17 through Q19 and resistors R25 through R27 have beenremoved, that transistors Q20, Q21 and Q22, and resistors R36, R37, andR38 have been added and that the Storage Columns have been divided intotwo groups where one group is connected to the collector of transistorQ20 through column Resistors R28 through R31 and the other group isconnected to the collector of transistor Q21 through Column ResistorsR32 through R35. Address line A4 controls transistors Q20, Q21, and Q22such that Q20 and Q21 are a complementary pair that controls theenabling of the left four lines or the right four lines of the Storagecolumns. Since a Storage Column is otherwise disabled by applying avoltage to that line (through an Addressing Row and a Column addressingRectifier) which results in a current equal to roughly the difference ofthe positive supply less 0.9 v divided by the Cathode Resistor value 1MΩ (4.1 μA if using a 5 v supply), wherever a line can be disabled bycutting off the current through the Column Resistor, that much currertwill be saved. These savings will become significant in much largerarrays having a very large number of Storage Columns. The limit on thenumber of address lines that will control this type of power reducingmeans for enabling Storage Columns relates to the complexity of thecircuit by increasing the number of transistors (a complex component)while reducing the number of rectifiers (a relatively less complexcomponent). One skilled in the art will recognize that this same type ofpower saving enabling means could also be created on the Storage Rows byusing PNP transistors to control the cutting off of current to thoseStorage Rows (through the Row Resistors).

Another variation might be to use differently made components. Forexample, in the above explanation, silicon rectifiers having a forwardvoltage of about 0.7 v and transistors having base-emitter forwardvoltages also of about 0.7 v were assumed. But, other types ofrectifiers and transistors could be used having lower or higher forwardvoltages. In another variation, the Storage Rectifiers used could be thebase-emitter junctions of NPN transistors (having all of theircollectors tied together in the same way one would tie together theoutputs of opened-collector gates in a logical AND configuration); thiswould make it possible to eliminate all of the Storage Bit SensingRectifiers, transistor Q1, resistor R9 and rectifiers D33, D34 and D35and instead sense the current sunk on the combined collectors. Since nomore than one Storage Rectifier will be conducting at any time, currentbeing sunk on the combined collectors would indicate that a StorageRectifier (a base-emitter junction) exists at the point of intersectionof the enabled Storage Row and the enabled Storage Column. Othervariations could include, memory cells comprising a fusible linkresulting in a One Time Programmable Read Only Memory (OTPROM) device(see U.S. Pat. Nos. 4,312,046 and 4,385,368), or memory cells comprisingcharge-storage devices to create a Random Access Memory (RAM) device(see U.S. Pat. Nos. 3,626,389 and 3,838,405).

The above description of the preferred embodiment makes reference to avariation on the resistive means—that of using “leaky” diodes. FIG. 12shows a plot depicting the voltage/current relationship of a typicaldiode, where the horizontal axis is voltage, V, and the vertical axis iscurrent, I. Moving right from the plot's origin, one can see that nosignificant current flows through the diode until the Forward Voltage,F, is reached. Moving left from the plot's origin, one can see that onlya small amount of leakage current flows until the Reverse BreakdownVoltage, R, is reached. However, there is a region, A, between theorigin and the point of the Reverse Breakdown Voltage where the devicebehaves similarly to a resistor.

FIG. 13 shows a variation wherein the resistive means comprises diodesthat are believed to operate in this resistor-like region. The diodebiasing circuit, A (which would typically not be constructed as a partof an integrated circuit comprising the remainder of the circuit shownin this figure), comprises circuitry for biasing a row of diodes, H, inthis resistor-like region for the row lines as well as circuitry forbiasing a row of diodes, J, in this resistor-like region for the columnlines. All of the diodes would be formed as a part of the sameintegrated circuit and would therefore have operating characteristicsthat are matched. On the row lines, the diodes, H, will be biasedbetween the voltage of a disabled row and the voltage present at theoutput of the operational amplifier, B. The operational amplifiercircuitry will ensure that the voltage across feedback diode D102 willbe the same as is across the diodes, H. As a result, the current throughdiodes, H, and diode D102 will be the same as a result of the devicematching. This is accomplished by pulling down point K in identicalfashion to when pulling down any of the row address lines (A0 through−A2). This ensures that the voltage on the anode of diode D103 willmatch the voltage on any one of the disabled row lines since anoperational amplifier operates (as one skilled in the art knows) suchthat the same voltage will be present at the ‘+’ and ‘−’ terminals innormal feedback mode. Current sources C and D have equal magnitude andensure that the same current flows through D102 and D103 and, therefore,that the voltage drop across D102 and D103 is matched; they could beconstructed as a part of a standard current mirror circuit. The resultis that the voltage at the anode of diode D102 matches the voltage onone of the disabled row lines, that the voltage on the anodes of diodesD86 through D93 matches the voltage at the anode of diode D102 (they areconnected to the row lines), and the cathodes of all the diodes D86through D93 as well as the cathode of diode D102 are at the same voltage(which is greater than that of the disabled row lines resulting in areverse voltage across all the diodes). Given that the reverse voltagedrop across diodes D86 through D93 is the same as that across diodeD102, the current leaking through the diodes D36 through D93 will be thesame as the current leaking through diode D102 (and controlled bycurrent source C) due to their matched operating characteristics. Thesame mechanism is essentially accomplished for the column line resistivemeans with via operational amplifier E, current sources F and G, diodesD94 through D101, feedback diode D104 and diode D105, but with oppositepolarity. Note that point L would be sourced in identical fashion to thesourcing of the column address lines (−A3 through A5).

FIG. 13 also shows a possible solution should the cumulative diodeleakage currents in extremely large arrays of Storage Rectifiers becomenoticeable. An additional Addressing Row, N, has been included. Noticethis row has a rectifier connecting it to every one of the StorageColumns and that asserting this row by pulling it to the positive supplywill disable the one remaining Storage Column that had been leftenabled. As a result, it is believed that one could detect the presenceof a Storage Rectifier at the point of intersection of the enabledStorage Row and Storage Column even with the existence of such leakagecurrents by sampling the level at the output both while asserting andnot asserting this Addressing Row, N. Since the presence of a StorageRectifier will result in a loading of the one enabled Storage Row byconnecting that row through the Storage Rectifier to the remainingenabled Storage Column, disabling that Storage Column would remove thisloading and result in a slightly higher voltage at the Output. However,if no Storage Rectifier is present, the level at the Output should notshow any significant change.

Other variations might include reversing the polarity and types of someof the components. Because of the symmetry of the DRS array, many of thetechniques shown in one area of the device can be implemented in theopposite area with only a reversal of polarities. for example, oneskilled in the art will recognize that The Storage Bit SensingRectifiers could be connected to the Storage Columns if transistor Q1was of the PNP type, rectifiers D33, D34, and D35 were reversed inpolarity and connected in series to ground instead of to the positivesupply, and resistor R9 was connected to the positive supply instead ofto ground; in this variation, the collector of transistor Q1 would be acurrent source instead of a current sink.

In another variation the means of row or column selection by disablingcertain rows or columns might be used in combination with otherselection means disclosed in the prior or subsequent art.

It is believed that Dual-addressed Rectifier Storage Arrays willtypically be fabricated as an integrated circuit; a possible layout ofthe Rows, the Columns, and the rectifiers are shown in FIGS. 6 through10 (the addressing transistors and resistors, the Row and ColumnResistors, and the connection pads to the chip have been omitted forclarity—the fabrication of these devices are well known to those skilledin the art). In FIG. 6, an N-type wafer is shown to be doped with P-typechannels which form the Rows. Next (FIG. 7) is shown that an oxide layeris grown and then (FIG. 8) openings corresponding to the rectifiers inthe circuit are etched through that oxide layer. The data stored in thedevice is programmed during this step—wherever a Storage Rectifier isdesired, a hole is etched through the oxide layer (it should be notedthat the pattern of the openings matches the pattern of the rectifiersas drawn in FIG. 3). FIG. 9 shows the chip with an aluminum metalizationlayer and finally (FIG. 10) shows the result of etching that aluminuminto vertical lines which form the Columns. Wherever the aluminumcontacts a doped region through one of the holes in the oxide layer, arectifier (of the type sometimes referred to as a metal-on-siliconjunction type or as a Schottky Diode type) is formed. The N-type wafersubstrate would be kept at the most negative voltage in the circuitthereby creating reverse biased p-n junction between the doped regionsand the substrate, the result of which is to electrically isolate thosegenerally parallel doped regions. The generally parallel metalizedregions which form the Columns are electrically isolated from each otherdue to their being formed upon the non-conducting oxide layer (exceptwhere they contact the doped regions through the holes in the oxidelayer). Where the aluminum Columns contact the P-type Rows, ametal-on-silicon junction rectifier is formed such that the current flow(where conventional current flow is the flow of holes, that is to say,current flowing from positive voltage potential to negative voltagepotential) is from the doped regions to the metalized regions when thejunction is forward biased. As shown in FIG. 10, space is available forthe manufacture of the addressing components and the Row and ColumnResistive means at the lower left corner of the chip and around theedges.

The addressing components might also be modified when constructing a DRSArray as an integrated circuit. The pair of resistors directly connectedbetween each address input and the bases of the two addressingtransistors could be replaced by a single resistor (as shown in FIG. 3,a single resistor could do the job of resistors R10 and R12, a singleresistor could do the job of resistors R13 and R15, and so on). Thosetransistors could be external to the integrated circuit form of the DRSArray.

A variation on the semiconductor manufacturing of a DRS Array might beto dope N-type regions into a P-type wafer thereby reversing thepolarity of the metal-on-silicon junction rectifiers (the Rows and theColumns would be reversed). Another variation would spread out theAddressing Columns across the width of the chip—alternating AddressingColumns with one or more Storage Columns—instead of grouping thoseAddressing Columns at the left side of the chip; this will spread outthose Lines carrying most of the current in the circuit thereby moreevenly distributing the power dissipation across the chip (the sametechnique could be done with the Rows). Another variation would be toconstruct the device with p-n junction rectifiers or a combination onmetal-on-silicon junction rectifiers and p-n junction rectifiers.

Another variation might enable programming the stored data during themetalization etching step. Referring to FIG. 11, an opening has beenetched through the oxide layer at every potential Storage Rectifierlocation. Programming of the stored data bits is accomplished when themetalization layer is etched. In those locations where a storageRectifier is desired, a metal connection is left during the metaletching step between the metal pad covering the opening in the oxidelayer and the metal Column; where no storage Rectifier is desired, thatmetal connection is etched away. It is believed that this approach willenable all of the semiconductor manufacturing steps, except the finalmetal etching step to be performed and that wafers so made could bestored safely under the protective metalized layer. In this way, waferscould be mass produced without regard to the data to be stored in thechip.

Economic concerns may drive several other possible variations on thesemiconductor manufacturing of a DRS Array. It is expected that asignificant part of the cost to manufacture these devices will be in thepackaging where the greater the number of electrical connections betweenthe package and the controlling device, the greater the cost of thatpackaging; a package with more leads will be more expensive and moreprone to mechanical failures. As a result, it is believed that stepswill be taken to reduce the number of package leads needed. One skilledin the art will quickly realize the circuitry needed to implement any ofthe following variations. One possibility would be to address the loweraddress lines directly but to retain the higher address linesinternally; in other words, the latch shown in FIG. 2 would beincorporated into the DRS Array integrated circuit. Another possibilitywould be to incorporate a shift-register where the address bits would beshifted into the device serially and retained thereby reducing thenumber of addressing leads to two (the shift-register serial input andthe shifting-clock). However, a more practical variation, shown in FIG.14, might be to incorporate both a counter and a shift register wherethe shift register would be used to enter an address onto the chip whichcould then be loaded into the counter. In this last variation of theserially loaded counter, the address would be retained within thecounter so the many address lines are essentially reduced to four: onefor the serial address input (S), one for clocking the shift register(K), one for clocking the counter (C), and one for loading the addressinto the counter from the shift register (L). One skilled in the artwill quickly realize the circuitry needed to implement any of thesevariations. One well skilled in the art will recognize that a reductionto three lines can be achieved here resulting in a total of sixconnections to the chip (three plus power, ground, and data out).

Finally, a variation on the digital logic device comprising one or moreDRS Arrays of which one or more may be removable which themselvescomprise the above mentioned serially loaded counter logic. By limitingthe manufacture of such devices to having output in analog format only,the risks to the makers of programming (e.g., music and video programs)will be reduced. With CD-ROM technology, the output from some CD-ROMreaders is in a digital format. As a result, any copy made will be ofthe same quality as the original. This potentially results insignificant lost revenue as the users of this technology could casuallymake copies for friends and relatives that cannot be distinguished fromthe originals (this was not the case with prior technologies such ascassette tapes and video tapes where each successive copy degradedsomewhat). By limiting the manufacture of devices comprising DRS Arraysthat are addressed via serially loaded counters to analog output only,the same degradation of copies will occur thereby reducing some of therisks to the makers of programming by causing the copies to be lessdesirable than the originals. While devices comprising DRS Arrays thatare addressed via serially loaded counters could be limited to analogoutput only, they could still include means for reading DRS Arrays inother formats (i.e., DRS Arrays directly addressed via many addresslines), however, devices comprising DRS Arrays that are directlyaddressed via many address lines and which give digital access to theinformation stored therein would not include means for reading DRSArrays that are addressed via serially loaded counters.

It is believed that minor flaws in the semiconductor wafer will mostlyimpact the operation of the metal-on-silicon junction rectifiers whenthey are reverse biased by lowering the reverse breakdown voltage. Sincethe DRS Arrays are expected to be operated at low voltage levels, largereverse voltages are considered unlikely in normal operation. As aresult, the impact of these minor flaws are not expected to impact theoperation of the device and high device manufacturing yields areanticipated. However, the addressing transistors will likely beadversely affected by such flaws. There will likely be a trade-offbetween the increased cost of manufacture resulting from lowered deviceyields (as a result of the impact of semiconductor flaws on theincreased complexity of the addressing circuit) and the savings onpackaging (as a result of reducing the number of device leads).

The selection of a line by disabling all undesired lines could beutilized in many related electronic devices. The rectifiers at thestorage locations could be fabricated as Light Emitting Diodes LED's)with such a rectifier present at every storage location. In this way,the device could be used as a display panel where a given display pixelcould be turned on by selecting that bit location; the display panelwould be scanned, selecting and illuminating bit locations in sequencewhile skipping bit locations that are to remain dark. Also, using atechnique such as pulse width modulation, which is well known to oneskilled in the art, one could even control the duration of a pulse oflight emitted at any given pixel location and thereby control theperception of the intensity of the light emitted.

The high expected storage densities come from the symmetry thedesign—the Storage Bit Sensing Rectifiers, The Addressing Rectifiers,and the Storage Rectifiers are all constructed in the same way. Theresult of this is that they can all be made at the same time with thesame semiconductor manufacturing steps. By using metal-on-siliconjunction rectifiers, the primary components in the circuit areessentially constructed vertically on the semiconductor's surfaceinstead of horizontally as might conventionally be done resulting in avery efficient use of the semiconductor “real estate”. The scaling up ofthe device is expected to be easily accomplished. For example, on a oneinch square chip, if the Anode Lines and the Cathode Lines are placed atroughly 0.45 micron center to center spacing, then a DRS Array that isroughly 65,536 by 65,536 Lines could be made. This is the equivalent ofabout 4,294,967,296 bits or about 536,870,912 bytes or about thecapacity of a present day CD ROM. State of the art technology at thetime of this writing is below 1 micron line widths. It is envisionedthat the present invention could be used anywhere that one would use aCD-ROM drive or player or anywhere a large amount of information isneeded.

The foregoing description of an example of the preferred embodiment ofthe invention and the variations thereon have been presented for thepurposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise forms disclosed.Many modifications and variations are possible in light of the aboveteaching. It is intended that the scope of the invention be limited notby this detailed description, but rather by the claims appended hereto.

1. A digital logic device comprising one or more electronic informationstorage means, and addressing means for accessing said storage means,wherein each said electronic information storage means comprises: aplurality of generally parallel conductive means; a second plurality ofgenerally parallel conductive means that is generally perpendicular toand overlapping with the first said plurality of generally parallelconductive means; a plurality of bits of potential information storagewhere a bit of said plurality of bits is present in the general vicinityof each point of intersection of each conductive means of the first saidplurality of generally parallel conductive means with each conductivemeans of the second said plurality of generally parallel conductivemeans, and where the state of any said bit is determined by the presenceor absence of a rectifying conductive means at each said generalvicinity of said point of intersection; means for selecting a conductivemeans of one plurality of generally parallel conductive means, and meansfor biasing the generally parallel conductive means of the otherplurality of generally parallel conductive means such that each saidrectifying conductive means present between a conductive means of saidbiased plurality of generally parallel conductive means to a conductivemeans of the other said plurality of generally parallel conductive meansis potentially forward biased; means for selecting a biased conductivemeans by electronically disabling conductive means within said biasedplurality of generally parallel conductive means by shifting the voltageof those biased conductive means that are to be disabled; and whereinsaid addressing means comprises: means for controlling said means forelectronically selecting conductive means of one said plurality ofgenerally parallel conductive means and for electronically selectingconductive means of the other said plurality of generally parallelconductive means.
 2. The digital logic device of claim 1, wherein saidmeans for selecting a conductive means of one plurality of generallyparallel conductive means comprises: means for biasing the generallyparallel conductive means of the said one plurality of generallyparallel conductive means such that each said rectifying conductivemeans present between a conductive means of said biased plurality ofgenerally parallel conductive means and a conductive means of the othersaid plurality of generally parallel conductive means is potentiallyforward biased; and means for selecting a biased conductive means byelectronically disabling conductive means within said biased pluralityof generally parallel conductive means by shifting the voltage of thosebiased conductive means that are to be disabled.
 3. The digital logicdevice of claim 1, further comprising means for detecting a conductedcurrent through said rectifying conductive means if present at saidpoint of intersection.
 4. The digital logic device of claim 1, whereinone of said plurality of generally parallel conductive means is aplurality of generally parallel doped regions within a semiconductormaterial.
 5. The digital logic device of claim 4, wherein the other ofsaid plurality of generally parallel conductive means is a plurality ofgenerally parallel metalized regions.
 6. The digital logic device ofclaim 1, wherein said addressing means comprises means to sequentiallyselect addressed locations.
 7. The digital logic device of claim 1,wherein said addressing means comprises means to randomly selectaddressed locations.
 8. The digital logic device of claim 1, furthercomprising display means for displaying alphanumeric or graphicinformation to its user.
 9. The digital logic device of claim 1, furthercomprising input means to enable its user to alter its operation. 10.The digital logic device of claim 1, wherein part or all of said onemore electronic storage means are removable or replaceable.
 11. Thedigital logic device of claim 1, wherein output from the device is in adigital format.
 12. The digital logic device of claim 1, wherein outputfrom the device is in an analog format.
 13. The digital logic device ofclaim 1, wherein output from the device is in either a digital format oran analog format.
 14. An electronic information storage devicecomprising: a plurality of generally parallel conductive means; a secondplurality of generally parallel conductive means that is generallyperpendicular to and overlapping with the first said plurality ofgenerally parallel conductive means; a plurality of bits of potentialinformation storage where a bit of said plurality of bits is present inthe general vicinity of each point of intersection of each conductivemeans of the first said plurality of generally parallel conductive meansand each conductive means of the second said plurality of generallyparallel conductive means, and where the state of any said bit isdetermined by the presence or absence of a rectifying conductive meansat each said general vicinity of said point of intersection; means forselecting a conductive means of one plurality of generally parallelconductive means, and means for biasing the generally parallelconductive means of the other plurality of generally parallel conductivemeans such that each said rectifying conductive means present between aconductive means of said biased plurality of generally parallelconductive means and a conductive means of the other said plurality ofgenerally parallel conductive means is potentially forward biased; andmeans for selecting a biased conductive means by electronicallydisabling conductive means within said biased plurality of generallyparallel conductive means by shifting the voltage of those biasedconductive means that are to be disabled.
 15. The storage device ofclaim 14, wherein said means for selecting a conductive means of oneplurality of generally parallel conductive means comprises: means forbiasing the generally parallel conductive means of the said oneplurality of generally parallel conductive means such that each saidrectifying conductive means present between a conductive means of saidbiased plurality of generally parallel conductive means and a conductivemeans of the other said plurality of generally parallel conductive meansis potentially forward biased; and means for selecting a biasedconductive means by electronically disabling conductive means withinsaid biased plurality of generally parallel conductive means by shiftingthe voltage of those biased conductive means that are to be disabled.16. The storage device of claim 14, further comprising means fordetecting a conducted current through said rectifying conductive meansif present at said point of intersection.
 17. The storage device ofclaim 14, wherein one of said plurality of generally parallel conductivemeans is a plurality of generally parallel doped regions within asemiconductor material.
 18. The storage device of claim 17, wherein saidrectifying conductive means between said plurality of generally paralleldoped regions and a plurality of generally parallel metalized regions isof the metal-on-semiconductor junction type.
 19. The storage device ofclaim 17, wherein said rectifying conductive means between saidplurality of generally parallel doped regions and a plurality ofgenerally parallel metalized regions is of the p-n junction type. 20.The storage device of claim 14, wherein one of said plurality ofgenerally parallel conductive means is a plurality of generally parallelmetalized regions.
 21. The storage device of claim 14, wherein saidrectifying conductive means is comprised by a transistor as thebase-emitter junction.
 22. The storage device of claim 14, furthercomprising means for retaining the address of the information to beaccessed.
 23. The storage device of claim 22, further comprising meansfor incrementing the retained address.
 24. The storage device of claim22, further comprising means for setting the retained address.
 25. Anelectronic information storage device comprising a plurality of storagemeans where each storage means comprises: a plurality of generallyparallel conductive means; a second plurality of generally parallelconductive means that is generally perpendicular to and overlapping withthe first said plurality of generally parallel conductive means; aplurality of bits of potential information storage where a bit of saidplurality of bits is present in the general vicinity of each point ofintersection of each conductive means of the first said plurality ofgenerally parallel conductive means and each conductive means of thesecond said plurality of generally parallel conductive means, and wherethe state of any said bit is determined by the presence or absence of arectifying conductive means at each said general vicinity of said pointof intersection; means for selecting a conductive means of one pluralityof generally parallel conductive means, and means for biasing thegenerally parallel conductive means of the other plurality of generallyparallel conductive means such that each said rectifying conductivemeans present between a conductive means of said biased plurality ofgenerally parallel conductive means and a conductive means of the othersaid plurality of generally parallel conductive means is potentiallyforward biased; and means for selecting a biased conductive means byelectronically disabling conductive means within said biased pluralityof generally parallel conductive means by shifting the voltage of thosebiased conductive means that are to be disabled; where at least one ofsaid plurality of generally parallel conductive means is common to morethan one said storage means.
 26. The storage device of claim 25, whereinsaid means for selecting a conductive means of one plurality ofgenerally parallel conductive means comprises: means for biasing thegenerally parallel conductive means of the said one plurality ofgenerally parallel conductive means such that each said rectifyingconductive means present between a conductive means of said biasedplurality of generally parallel conductive means and a conductive meansof the other said plurality of generally parallel conductive means ispotentially forward biased; and means for selecting a biased conductivemeans by electronically disabling conductive means within said biasedplurality of generally parallel conductive means by shifting the voltageof those biased conductive means that are to be disabled.
 27. Asemiconductor information storage device comprising: a plurality ofgenerally parallel conductive means; a second plurality of generallyparallel conductive means that is generally perpendicular to andoverlapping with the first said plurality of generally parallelconductive means where one of said two pluralities of generally parallelconductive means is generally a surface layer of the semiconductor; anda plurality of bits of potential information storage where a bit of saidplurality of bits is present in the general vicinity of each point ofintersection of each conductive means of the first said plurality ofgenerally parallel conductive means and each conductive means of thesecond said plurality of generally parallel conductive means, and wherethe state of any said bit is determined by the presence or absence of arectifying conductive means at each said general vicinity of said pointof intersection, and where any said presence or absence of a rectifyingconductive means is determined by the leaving in place or the removal,respectively, of a portion of the surface layer conductive means.
 28. Anelectronic array of selectable points comprising: a plurality ofconductive means; a second plurality of conductive means; a plurality ofselectable points where a point of said plurality of selectable pointsis present in the general vicinity of each point of intersection of eachconductive means of the first said plurality of conductive means andeach conductive means of the second said plurality of conductive means;means for selecting a conductive means of one plurality of conductivemeans, and means for biasing the conductive means of the other pluralityof conductive means such that each said selectable point present betweena conductive means of said biased plurality of conductive means and aconductive means of the other said plurality of conductive means ispotentially forward biased; and means for selecting a biased conductivemeans by electronically disabling conductive means within said biasedplurality of conductive means by shifting the voltage of those biasedconductive means that are to be disabled.
 29. The electronic array ofselectable points of claim 28, wherein said means for selecting aconductive means of one plurality of generally parallel conductive meanscomprises: means for biasing the conductive means of the said oneplurality of conductive means such that each said selectable pointpresent between a conductive means of said biased plurality ofconductive means and a conductive means of the other said plurality ofconductive means is potentially forward biased; and means for selectinga biased conductive means by electronically disabling conductive meanswithin said biased plurality of conductive means by shifting the voltageof those biased conductive means that are to be disabled.
 30. Theelectronic array of selectable points of claim 28, wherein said eachselectable point comprises a light emitting diode (LED) which will emitlight when forward biased.
 31. An information-storage circuit, thecircuit comprising: a plurality of row storage lines; a plurality ofcolumn storage lines overlapping the plurality of row storage lines; aplurality of storage locations, wherein each storage location isdisposed proximate to a point of intersection between a row storage lineand a column storage line; a plurality of nonlinear storage elements,wherein each nonlinear storage element is disposed at a storagelocation; a plurality of row decoder lines electrically connected to theplurality of row storage lines; a plurality of column decoder lineselectrically connected to the plurality of column storage lines; aplurality of nonlinear row address elements connected to the pluralityof row decoder lines; a plurality of nonlinear column address elementsconnected to the plurality of column decoder lines; a plurality of rowaddress lines connected to the plurality of nonlinear row addresselements, wherein a number of the row address lines is less than anumber of the row decoder lines; a plurality of column address linesconnected to the plurality of nonlinear column address elements, whereina number of the column address lines is less than a number of the columndecoder lines; wherein a row address applied to the plurality of rowaddress lines causes the plurality of nonlinear row address elements toselect a row decoder line, the selected row decoder line selects a rowstorage line to which it is connected, a column address applied to theplurality of column address lines causes the plurality of nonlinearcolumn address elements to select a column decoder line, the selectedcolumn decoder line selects a column storage line to which it isconnected, and the intersection between the selected row storage lineand the selected column storage line comprises the storage locationdefined by the row address and the column address.
 32. Theinformation-storage circuit of claim 31, wherein each of the pluralityof nonlinear storage elements comprises a diode.
 33. Theinformation-storage circuit of claim 31, wherein each of the pluralityof nonlinear row address elements comprises a diode.
 34. Theinformation-storage circuit of claim 31, wherein each of the pluralityof nonlinear column address elements comprises a diode.
 35. Theinformation-storage circuit of claim 31, wherein at least one storagelocation is programmed with data comprising at least one of music,video, computer software, a computer application, reference data, text,or a diagram.
 36. The information-storage circuit of claim 31, furthercomprising logic circuitry connected to the plurality of column addresslines configured to apply a plurality of column addresses to theplurality of column address lines simultaneously.
 37. Theinformation-storage circuit of claim 31, further comprising logiccircuitry connected to the plurality of column address lines configuredto substantially halt the flow of electrical current to at least one ofthe plurality of column address lines.
 38. The information-storagecircuit of claim 31, wherein the circuit is disposed within a removablememory storage device.
 39. The information-storage circuit of claim 31,further comprising counter circuitry connected to at least one of theplurality of row address lines or the plurality of column address lines.40. The information-storage circuit of claim 31, further comprisingshift register circuitry connected to at least one of the plurality ofrow address lines or the plurality of column address lines.
 41. Theinformation-storage circuit of claim 40, further comprising countercircuitry connected to and disposed between the shift register circuitryand at least one of the plurality of row address lines or the pluralityof column address lines.
 42. The information-storage circuit of claim41, wherein the shift register circuitry loads a row address into thecounter circuitry, and the counter circuitry applies the row address toat least one of the plurality of row address lines.
 43. Theinformation-storage circuit of claim 31, wherein each of the pluralityof nonlinear storage elements comprises a programmable material.
 44. Theinformation-storage circuit of claim 43, wherein said programmablematerial comprises a fusible link.
 45. The information-storage circuitof claim 43, wherein said programmable material comprises acharge-storage material.
 46. The information-storage circuit of claim31, wherein a center-to-center distance between the nonlinear storageelements is less than approximately 0.45 microns.
 47. Theinformation-storage circuit of claim 31, further comprising, disposedaround the plurality of storage locations, a package configured tointerface with an electronic device.
 48. The information-storage deviceof claim 47, further comprising interface logic circuitry connected toat least one of the plurality of row storage lines or the plurality ofcolumn storage lines.
 49. The information-storage device of claim 47,wherein the package is connected to an electronic device selected fromthe group consisting of a computer, a microprocessor, a microcomputerchip, and a digital logic device.
 50. The information-storage circuit ofclaim 47, wherein at least one storage location is programmed with datacomprising at least one of music, video, computer software, a computerapplication, reference data, text, or a diagram.
 51. Theinformation-storage device of claim 47, wherein the package is removableand interchangeable to the electronic device.
 52. Theinformation-storage device of claim 51, further comprising interfacelogic circuitry connected to at least one of the plurality of rowstorage lines or the plurality of column storage lines, wherein at leastone storage location is programmed with data comprising at least one ofmusic, video, computer software, a computer application, reference data,text, or a diagram.